// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:13 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  pcs_raw_cmn_creg.v
//
//  Control registers local to Raw PCS common module
//
//  Original Author: Chris Jones
//  Current Owner:   Ameer Youssef
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2013 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: spagnuol $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_cmn_creg.v $
//    $DateTime: 2015/06/29 14:33:42 $
//    $Revision: #9 $
//
////////////////////////////////////////////////////////////////////////////// 

`include "dwc_e12mp_phy_x4_ns_cr_macros.v"
`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_cmn_creg (
output wire [7:0]                 cr_cmn_sel,
output wire [31:0]                cr_cmn_aon_sel,

// Global CR control bus
//
input  wire                       cr_clk,
input  wire                       cr_rst,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr_addr
);

// RAW CMN
//
wire [`DWC_E12MP_X4NS_CR_BANK_DEPTH-1:0] cr_decode_sel_0;
assign cr_cmn_sel = cr_decode_sel_0[7:0];
dwc_e12mp_phy_x4_ns_pcs_raw_cr_decode #(.CR_TYPE(`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_CMN),
                    .BCAST_TYPE(`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_CMN),
                    .CR_BANK(3'h0))
cr_dec_pcs_raw_cmn (
  .cr_sel       (cr_decode_sel_0),
  .cr_bank_sel  (),
  .cr_chan_addr (4'h0),
  .cr_clk       (cr_clk),
  .cr_rst       (cr_rst),
  .cr_addr      (cr_addr)
);

wire [`DWC_E12MP_X4NS_CR_BANK_DEPTH-1:0] cr_decode_sel_1;
assign cr_cmn_aon_sel = cr_decode_sel_1[31:0];
dwc_e12mp_phy_x4_ns_pcs_raw_cr_decode #(.CR_TYPE(`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_CMN),
                    .BCAST_TYPE(`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_CMN),
                    .CR_BANK(3'h1))
cr_dec_pcs_raw_aon_cmn (
  .cr_sel       (cr_decode_sel_1),
  .cr_bank_sel  (),
  .cr_chan_addr (4'h0),
  .cr_clk       (cr_clk),
  .cr_rst       (cr_rst),
  .cr_addr      (cr_addr)
);

endmodule
